Field of the Invention
The invention lies in the field of semiconductors. The present invention relates to a semiconductor memory configuration having word lines and bit lines. Some bit lines are routed over a memory-cell area. Bit lines with a twist run alongside bit lines without a twist, and one bit-line pair with a twist has contacts for one bit line to be crossed over by the other bit line of the pair in a further plane that is different from the bit-line plane.
Conventionally, bit lines are routed over memory-cell areas with a bit-line twist and without a bit-line twist. A bit-line twist has the advantage that the two bit lines that cross each other through the twist are symmetrically coupled capacitively such that possible interference signals cancel each other. In addition, coupling in from adjacent lines is also canceled if "folded" bit lines are involved.
The crossing over of two bit lines in a twist assumes that one of the bit lines is routed over the other bit line at a distance and in an electrically insulated manner. The crossover can be done, for example, by raising one bit line (in relation to the other bit line) in the crossover area into the word-line plane through contacts, such that in the crossover area one bit line runs in the word-line plane, while the other bit line remains on the bit-line plane.
Adjacent bit lines should influence each other as little as possible, that is to say the electrical coupling between such adjacent bit lines should be reduced as far as possible. The reduction can be done by routing the bit lines with a large spacing and without a twist or crossover in relation to one another. However, such a large spacing is necessarily associated with a considerably increased area requirement for the memory-cell area.
In order to avoid the large spacing, the above mentioned twist is introduced. Then, the bit lines can run more closely alongside one another, thus, canceling the interference introduced by the capacitive coupling that is necessarily present as a result of the twist. At present, preference is given to semiconductor memory configurations in which bit lines are provided in pairs, without a twist and with a twist. Such preference means that two bit lines without a twist follow two bit lines with a twist. It has been shown that such a configuration of the bit lines achieves optimization with regard to reducing the effects of the capacitive coupling arising from the twist of each second bit-line pair, simplifies the circuit structure arising from the necessary crossovers for each second pair, and reduces the area required.
However, one disadvantage of configuring a semiconductor memory as set forth above is that in the word-line plane the individual word lines experience different proximity effects at different locations because it is only in the area of the bit-line pairs with a twist that the one bit lines, with their contacts, are routed into the word-line plane. Therefore, different and inhomogeneous affects on the word lines occur in the crossover area of the bit lines in an undesired way.